The invention is generally related to integrated circuit fabrication, and more particularly, to the fabrication of metal-insulator-metal (MIM) capacitor structures in integrated circuits.
Reduced circuit area is an economic driver of the microelectronics revolution. Integrated circuits, or chips, continue to increase in circuit density due to reduced sizes of circuit components made possible through the implementation of smaller and smaller circuit design rules. As more and more components are designed into an integrated circuit, the complexity of the integrated circuit is increased, thereby enabling greater functionality in the circuit. Moreover, functions that were once performed by multiple integrated circuits can often be integrated together onto the same integrated circuit, thereby reducing costs, power consumption, and size, while improving speed and interconnectivity.
In addition, other components such as capacitors, inductors, resistors, and other types of passive components are increasingly integrated into integrated circuits, thereby eliminating the need to incorporate separate, discrete components in a circuit design that otherwise increase circuit size, power consumption and cost. Both the demands of smaller circuit design rules, and the desire to incorporate various passive circuit components in an integrated circuit, however, has demanded new materials, new structures and new processing techniques to be incorporated into the integrated circuit fabrication process.
One type of passive component that is increasingly incorporated into many integrated circuit designs is a metal-insulator-metal (MIM) capacitor, which typically incorporates a stacked arrangement of materials that includes, in the least, top and bottom conductive electrodes incorporating a conductive material, and an intermediate insulator layer incorporating a dielectric material. Typically, a MIM capacitor is fabricated between the outermost metal layers in an integrated circuit (e.g., between the M5 and M6 layers), which orients the capacitor relatively far from the underlying semiconductor substrate, such that parasitic capacitance effects with the substrate are minimized.
MIM capacitors are often utilized, for example, in high frequency (e.g., RF) telecommunications applications such as in cell phones and other wireless devices, as well as other telecommunications products. Often, MIM capacitors are used to provide various functions in an integrated circuit, e.g., decoupling with a power supply, analog functions such as analog-to-digital conversions and filtering, and termination of transmission lines. Decoupling applications generally have relatively loose leakage current requirements, whereas analog applications, such as analog-to-digital converters (ADC""s), typically require closer capacitor matching and relatively good voltage linearity. Moreover, in many telecommunications applications, particularly in handheld applications, low loss and relatively small temperature linearity are desired.
Given the ever-present desire to reduce the sizes of components in an integrated circuit, it is desirable to minimize the circuit area occupied by MIM capacitors. To provide a desired capacitance from a MIM capacitor within a smaller circuit area, therefore, an increase in the capacitance density of the capacitor (which based upon present design rules is typically expressed in terms of femtofarads per square micrometer (fF/xcexcm2)) is required.
Conventional approaches to increasing MIM capacitor capacitance density have typically focused upon using high dielectric constant (K) dielectric materials in the insulator layer of a MIM capacitor, decreasing insulator layer thickness and/or utilizing structure geometries that increase perimeter (which increases fringe and lateral capacitance effects).
For example, high dielectric constant materials such as tantalum pentoxide, tantalum oxynitride, silicon nitride, barium strontium titanate (BST), lead zirconium titanate, and hafnium oxide have been used in some conventional MIM capacitor designs. Furthermore, various process improvements have been utilized to deposit such materials with reduced thicknesses, and without inducing short circuits between the electrodes of the capacitor design.
In addition, some MIM capacitor designs have relied upon multiple xe2x80x9cfingersxe2x80x9d forming one of the electrodes of a design. The multiple fingers extend generally parallel one another and incorporate an increased perimeter compared to a single contiguous electrode occupying the same circuit area.
Nonetheless, despite the improvements made in conventional MIM capacitor designs, many such designs are limited to at most about 1 fF/xcexcm2. At this density, however, capacitors providing the necessary capacitance for many applications (e.g., many RF applications) are inordinately large, particularly for more advanced design rules. As an example, at 1 fF/xcexcm2, a 100 nF capacitor would require a circuit area of approximately 1 cm per side, which, when used in connection with technology such as a 0.25 xcexcm RF BiCMOS technology, results in a width that is approximately 40,000 times the minimum feature size for the integrated circuit.
Therefore, a significant need continues to exist in the art for a manner of improving the capacitance density in a MIM capacitor structure.
Another difficulty experienced in connection with MIM capacitor fabrication is oxidation of the bottom electrode during fabrication. Particularly when electrode materials such as titanium nitride (TiN) are used, oxidation of the electrode prior to deposition of the insulator layer can occur and form titanium oxides that cause current leakage. Prior attempts to inhibit oxidation include, for example, depositing the insulator layer in the same tool in which the electrode material is deposited. However, by depositing both layers in the same tool, patterning and etching of both layers must generally occur together, requiring the insulator layer to have the same layout as the bottom electrode. Furthermore, close coupling of the bottom electrode and dielectric film depositions does not guarantee a clean interface between the materials.
Therefore, a significant need also exists in the art for a manner of inhibiting the formation of oxidation on a bottom electrode of a MIM capacitor structure.
Yet another difficulty experienced in connection with MIM capacitor fabrication is that of patterning and etching the MIM capacitor structure in connection with aluminum-based circuit interconnects. In particular, whenever aluminum or aluminum alloy interconnects, as are commonly used in the metal layers of an integrated circuit, are exposed to etching chemistry such as CCl4, BCl3, Cl2, etc., aluminum chloride is often generated as a byproduct thereof, necessitating the use of an additional aluminum polymer removal step to clean the partially-fabricated integrated circuit. Adding such a step increases processing time and expense, and may not remove all chlorine (Cl) containing compounds that can cause Al corrosion.
Therefore, a significant need also exists in the art for a manner of etching a MIM capacitor structure without undue exposure of aluminum interconnects to chlorine chemistry.
The invention addresses these and other problems associated with the prior art by providing in one aspect a Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit in which a sidewall spacer extends along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. By orienting a sidewall spacer, with a conductive layer that is physically separated from a top electrode, along the channel, it has been found that lateral capacitance effects between the pair of legs that face the channel are substantially increased, resulting in substantial improvements in overall capacitance density for the MIM capacitor structure.
While other manners of fabricating a sidewall spacer may be used consistent with the invention, one suitable manner includes forming first and second bottom electrodes that extend generally parallel to one another and defining a channel therebetween, depositing an insulator layer over the first and second bottom electrodes and in the channel, depositing a conductive layer over the insulator layer, and etching the deposited conductive and insulator layers. Etching these layers results in the definition of first and second top electrodes that oppose the first and second bottom electrodes, as well as a physical separation between a portion of the conductive layer in the channel and the first and second top electrodes.
The invention also addresses in another aspect a number of improvements to the process of making MIM capacitor structures. For example, one aspect of the invention addresses the difficulties associated with oxidation of the bottom electrode of a MIM capacitor structure by providing a MIM capacitor structure and method of fabricating the same in an integrated circuit in which a surface of the bottom electrode is ammonia plasma treated. As another example, another aspect of the invention addresses the difficulties associated with the exposure of aluminum interconnects to etching chemistry, by utilizing a multi-rate etching process to etch the top electrode and insulator layer of an MIM structure, using a first, higher rate to perform an anisotropic etch up to a point proximate an interface between the conductive and dielectric materials respectively defining the top electrode and insulator layer of the MIM structure, and then using a second, lower rate to perform an anisotropic etch to a point proximate an etch stop layer defined on the bottom electrode of the MIM structure. Through the use of an etch stop layer, underlying aluminum interconnects are protected from undue exposure to etching chemistry, thus eliminating in many instances the need for the aluminum polymer removal and related cleaning processes.
These and other advantages and features, which characterize the invention, are set forth in the claims annexed hereto and forming a further part hereof. However, for a better understanding of the invention, and of the advantages and objectives attained through its use, reference should be made to the Drawings, and to the accompanying descriptive matter, in which there is described exemplary embodiments of the invention.